Many modern processors utilize a pipeline within the processor for greater efficiency. With the use of a pipeline, a task is subdivided into a number of sequential subtasks. The division of a task into sequential subtasks allows fetching, decoding, and execution of a number of program instructions at any given time. Therefore, at any particular time, several instructions may be processed in various stages at the pipeline. Many such processors include a pipeline having a decode stage. At the decode stage of a pipeline, an instruction obtained from program memory is decoded so that the instruction may be executed. After an instruction is decoded, it is not necessary to store the instruction within the processor. However, until the instruction is decoded, the instruction obtained from program memory must be stored. In order to store the instruction until it has been decoded, many processors utilize an instruction buffer.
Conventionally, an instruction buffer includes enough registers to store a number of instructions equal to the number of stages up to and including the decode stage. For example, if a pipeline has a prefetch, a fetch, and a decode stage as its first three stages, the associated instruction buffer would have three registers for storing three instructions. This number of registers in an instruction buffer has been conventionally used because it allows retention of instructions that are being obtained when it is determined that the decode stage is stalled.
Although the use of an instruction buffer allows resuming of processing without loss of information, it is not without its disadvantages. For example, as the size of common instruction fetches increases, each register within the instruction buffer grows in size, which requires additional silicon area.